(1) Field of the Invention
This invention relates to a semiconductor memory and a method for controlling such a semiconductor memory and, more particularly, to a semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface and a method for controlling such a semiconductor memory.
(2) Description of the Related Art
In recent years attention has been riveted to DRAMs (pseudo SRAMs), which use a DRAM cell array and which have an SRAM interface, as memories most suitable for cellular phones etc. because of low power consumption, the feasibility of large storage capacity, cheapness, and so on.
On the other hand, synchronous DRAMs (SDRAMs) in which a memory bus operates in synchronization with a clock signal having a certain period have been used as memories in personal computers (PCs) and the like.
An operation mode of a pseudo SRAM or an SDRAM is set by a mode setting control circuit including a mode register described later. Setting an operation mode includes setting the number of megabytes of the entire memory chip to be refreshed (setting partial mode) and setting the number of clocks after a command being input after which the reading or writing of data is begun (setting latency).
One of operation modes of an SDRAM is burst mode. In burst mode, data is continuously written or read in synchronization with a clock signal. To set burst mode, burst length BL, being the number of times data is output or input, corresponding to one access command and the like are set on the basis of an external signal.
With SDRAMs a dedicated command called a mode register set command has been used in conventional methods for controlling a mode register (for example, refer to Japanese unexamined Patent Publication No. 2000-011652 (the paragraph number [0013] and FIG. 1)). With pseudo SRAMs, the method of preparing a dedicated command input to a dedicated pin or the method of combining a legal command, such as a read command or a write command, a specific address, and a specific data pattern has been used. In addition, the method of combining illegal commands not recognized as commands or the method of combining a legal command and a specific address can be used.
With pseudo SRAMs, however, setting a mode register by combining illegal commands will necessitate a change on the controller side. This causes a problem with compatibility with pseudo SRAMs used only in non-burst mode.
The method of preparing a dedicated command input to a dedicated pin will also necessitate a change on the controller side. Moreover, the size of a chip may increase.
The method of combining legal commands will cause the following problem in burst mode. When a command is input once at write or read operation time in burst mode, data with burst length BL set in a mode register will be input or output in synchronization with a clock signal. Therefore, to continuously input commands, each time interrupt operation must be performed. This increases the scale of circuits, resulting in an increase in the area of a chip.
Therefore, it has been difficult to use conventional pseudo SRAMs in burst mode.